Laser annealing (also called laser spike annealing or laser thermal processing) is used in semiconductor manufacturing for a variety of applications, including for activating dopants in select regions of devices (structures) formed in a semiconductor wafer when forming active microcircuits such as transistors.
One form of laser annealing uses a scanned laser beam (“laser annealing beam”) to heat the surface of the wafer to a temperature (the “annealing temperature”) for a time long enough to activate the dopants in the semiconductor structures (e.g., source and drain regions) but short enough to prevent substantial dopant diffusion. The time that the wafer surface is at the annealing temperature is determined by the power density of the laser annealing beam, as well as the exposure time, which is given by the width of the beam along the scan direction divided by the velocity at which the laser annealing beam is scanned (the “scan velocity”).
Typical semiconductor processing requirements call for the annealing temperature to be between 400° C. and 1,300° C., with a temperature uniformity of +/−3° C. To achieve this degree of temperature uniformity, the laser annealing beam needs to have a relatively uniform intensity in the cross-scan direction, which under most conditions represents less than a +/−5% intensity variation.
However, even when the laser annealing beam is made spatially very uniform, feedback to the laser is required to ensure that the annealing temperature remains uniform to within the stated tolerance. Local emissivity variations on patterned wafers can cause a temperature measurement error when the system cannot distinguish between a change in emission due to true temperature change and a local change in emissivity. For most logic device wafers, the thickness and composition of the patterned regions is such that the deviation in pattern emissivity from bulk silicon is relatively small.
For other types of device wafers, the variations in emissivity can be substantial. For example, memory wafers have thick metal lines. Also, certain logic wafers include a silicide step wherein the patterned regions have a relatively thick metal-silicide (e.g., NiSi). In both of these cases, the variation in thermal emission from the emissivity variations is large. Consequently, as the laser annealing beam scans such wafers, the amplitude and time-frequency of the pattern-induced emission variation is such that the temperature control system can become unstable.
Re-tuning the temperature control system to respond to emission spikes would cause the laser power to be modulated in response to emissivity variations, and not temperature variations. As a result, the laser annealing system must process silicide and memory wafers in open loop (constant laser power) condition, which limits the temperature uniformity performance of the laser anneal due to the uncompensated effects such as laser power density fluctuation and/or variation in the local substrate temperature.
This in turn limits the maximum safe annealing temperature. The annealing temperature needs to be kept below the damage threshold temperature of the wafer. The wider distribution of anneal temperatures under open-loop processing requires a reduction in the mean anneal temperature to keep the extremes of the anneal temperature distribution below the damage threshold. This presents a process compromise when (as is the case in most spike anneal process applications) a higher anneal temperature (below damage threshold) produces a superior process result